AMD has brought out its Spartan UltraScale+ FPGA family, the newest addition to its Cost-Optimised FPGAs and adaptive SoCs.
The family offers up to 572 I/Os and voltage support up to 3.3V, enabling any-to-any connectivity for edge sensing and control applications.
The 16nm fabric and support for a wide array of packaging, starting as small as 10x10mm, provide high I/O density in an ultra-compact footprint.
The family is estimated to offer up to a 30% reduction in power compared to the 28nm Artix 7 family, through 16nm FinFET technology and hardened connectivity.
They are the first AMD UltraScale+ FPGAs with a hardened LPDDR5 memory controller and PCIe Gen4 x8 support, providing both power efficiency and future-ready capabilities for customers.
Security features are:
Support for Post-Quantum Cryptography with NIST-approved algorithms offers state-of-the-art IP protection against evolving cyber-attacks and threats. A physical unclonable function provides each device with a unique fingerprint for added security.
PPK/SPK key support helps manage obsolete or compromised security keys while differential power analysis helps protect against side-channel attacks. The devices contain a permanent tamper penalty to further protect against misuse.
Enhanced single-event upset performance helps fast and secure configuration with increased reliability for customers.
All AMD’s FPGAs and adaptive SoCs are supported by the Vivado Design Suite and Vitis Unified Software Platform, allowing hardware and software designers to leverage the productivity benefits of these tools and included IPs via a single designer cockpit from design to verification.
Spartan UltraScale+ FPGA family sampling and evaluation kits are expected to be available in the first half of 2025.
Documentation is available today with tools support starting with the AMD Vivado Design Suite in the fourth quarter of 2024.
