AI delivers better chips

Recent customers ST  STMicroelectronics and SK hynix have been using reinforcement learning-enabled design tools on cloud and on-premise.

Customer results are said to include a more than 3x productivity increase, up to 25% lower total power and significant reduction in die size. First 100 Tape-outs

“Using the Synopsys design system on Microsoft Azure, we increased PPA exploration productivity by more than 3x, allowing us fast implementation of a new Arm core, while exceeding power, performance and area goals,” says Philippe d’Audigier, SoC hardware design director at ST.

Traditional design space exploration has been a highly labour-intensive effort, typically requiring months of experimentation.

Using AI technology, Synopsys searches design spaces autonomously to discover optimal PPA solutions, massively scaling the exploration of choices in chip design workflows and automating many menial tasks.

“Delivering high-performance, robust memory products at industry-leading volumes demands intensive optimization, which has traditionally been highly human intensive,” says Junhyun Chun, head of SoC at SK hynix. ” in a recent project delivered a 15% cell area reduction and a 5% die shrink.”

“AI’s ability to explore broader design spaces is accelerating our customers’ relentless drive towards better PPA and higher productivity with fewer engineering resources,” said Shankar “In every case, designers are seeing significant gains from optimized designs delivering better results and faster time-to-market,” says Shankar Krishnamoorthy eDA GM at Synopsys.

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