Hardware isolation and virtualisation are provided to allow sharing of on-die hardware between different code blocks without interaction “to support the consolidation of cross-vehicle electronic control units in vehicle central compute applications”, said NXP. “Vehicle functions can be independently managed, including fault handling and reset. They can receive independent software over-the-air updates, which is a crucial capability for software-defined vehicles to enhance their functionality over time.”
The IC is S32N55, the first of a forthcoming S32N family of compatible processors with different capabilities, intended to be the centre of NXP’s ‘S32 CoreRide’ software-defined vehicle architecture.
“Through software-defined, hardware-enforced isolation, S32N55 can host dozens of vehicle functions with different levels of criticality, while providing freedom from interference between them,” it said.
The cores can operate in split or lock-step mode to support functional safety levels up to ISO 26262 ASIL D.
Two auxiliary pairs of lockstep Cortex-M7 cores are included for system and communication management, the 48Mbyte of ram is tightly-coupled for low-latency accesses.
“A firewalled hardware security engine provides a root-of-trust for secure boot, security services and key management,” said NXP. “Functional safety and security are supported with memory error correction and in-line cryptography.”
Memory can be expanded through LPDDR4X/5/5X dram, LPDDR4X flash and NAND/NOR flash interfaces.
Interface periphearls include a TSN (time-sensitive networking) 2.5Gbit/s Ethernet switch, a CAN hub for internally routing 24 CAN FD buses, 4x CAN XL and PCI Express Gen 4.
A power management IC, FS04, has been designed alongside the processor to support ASIL D functional safety.
S32N55 is sampling to selected customers.
Find NXP in two places at Embedded World: hall 4A stand 222 and hall 3A stand 128, and find a brief S32N55 product page here
