Rapid Silicon readies first two FPGAs for Q1

The first two chips in the six-chip family calked Gemini are the smallest and largest members of the family – a 50,000 Logic Cell device and a 250,000 Logic Cell device.

The other four chips in the family are yet to be announced. The Gemini range offers 400 to 550 I/Os, dual-port block RAM and DSP slices. It uses CPUs from Arm and Andes.

“Customers are looking for innovative ways to programme FPGAs, reduce support load by leveraging the open-source ecosystem of active expertise and development engineers, and shorten time-to-market,” says Naveed Sherwani (pictured) Chairman and CEO of Rapid Silicon, “with  open-source software, Rapid Silicon is removing the barriers and providing its customers with a robust end-to-end FPGA design workflow. The open-source software enables users to design complex applications quickly and efficiently on our FPGA devices.”

Rapid was founded in 2021 in Los Gatos with a seed round of $15 million. It has staff in Pakistan, Malaysia and Armenia.

Earlier this year, it closed the first $15 million tranche of a Series A round. It is expect a second 15 million tranche to close this quarter.

Both rounds include Cambian Capital Partners and Chengwei Capital  as investors.

The CEO Naveed Sherwani was CEO of SiFive. The CTO is P.E. Gaillardon, a professor at Utah University.

Sherwani has founded multiple companies including STI, Intel Micro-electronics, Open-Silicon, Brite Semiconductor, Anasage, HighSilicon, HighBitCoin, PeerNova, StarFive. LeapFive, ChinaFive, SemiFive, Lampro Mellon, Global Semiconductor Group, GS Microelectronics and Rapid Silicon.

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