UFS 4.0 incorporates MIPI M-PHY 5.0 and UniPro 2.0 and supports theoretical interface speeds of 
up to 23.2Gbps per lane or 46.4Gbps per device. UFS 4.0 is backward compatible with UFS 3.1.
Key Features include:
- Performance improvement over previous generation[3]: +18% sequential write, +30% random write and +13% random read
- Supports High Speed Link Startup Sequence (HS-LSS) features: With conventional UFS, Link Startup (M-PHY and UniPro initialization sequence) between device and host is performed at low-speed PWM-G1 (3~9Mbps[4]), but with HS-LSS, it can be performed at a faster HS-G1 Rate A (1248Mbps). This is expected to reduce the time for Link Startup by approximately 70% compared to the conventional method.
- Enhances security: By utilizing Advanced RPMB (Replay Protected Memory Block) for faster read and write access to security data, such as user credentials on RPMB area, and RPMB Purge to ensure discarded data may be sanitized securely and rapidly.
- Supports Extended Initiator ID (Ext-IID): Intended to be used with Multi Circular Queue (MCQ) at the UFS 4.0 host controller for improved random performance.
More at:
https://www.kioxia.com/en-jp/business/memory/mlc-nand/ufs4.htm
