sureCore’s cryogenic SRAM is a building block for any digital sub-system, that is capable of operating from 77K (-196°C) down to the near absolute zero temperatures needed by Quantum Computers (QCs). Standard cell and IO cell libraries have been re-characterised for operation at cryogenic temperatures thereby enabling an industry standard RTL to GDSII physical design flow to be readily adopted.
A barrier to QC scaling is being able to collocate ever increasingly complex control electronics close to the qubits that must be housed at cryogenic temperatures in a cryostat. In doing so, it is essential that the control chip power consumption is kept as low as possible to ensure that excess heat is kept to a minimum, so it does not cause additional thermal load on the cryostat. Here, sureCore’s low power design expertise proved pivotal.
Current QC designs have the control electronics located outside the cryostat as modern semiconductor technology is only qualified to work down to -40°C. As the temperature is reduced close to absolute zero, the operating characteristics of the transistors change markedly. Measuring, understanding and modelling this behavioural change over the past months has culminated in this IP demonstrator chip that will showcase the potential to build cryogenic interface chips that can control and monitor qubits at cryogenic temperatures.
Paul Wells, sureCore’s CEO, explained, “Currently, expensive bulky cabling connects room temperature control electronics to the qubits housed in the cryostat,” says sureCore CEO Paul Wells, “enabling QC developers to be able to exploit the fabless design paradigm and create their own custom cryogenic control SoCs, which can be housed with the qubits inside the cryostat, is a game-changer that will rapidly enable QC scaling. Immediate benefits include cost, size and, most importantly, latency reduction. The next step will be characterising the demonstrator chip at cryo temperatures to further refine and validate the models to help improve the performance.”
