Agile Analog provided XMOS with a comprehensive range of analogue IP blocks integrated into a single macro, incorporating the XMOS digital control system to form a complete always-on subsystem.
Agile Analog’s ultra-low-power IP included its configurable bandgap reference (agileREF), power-on-reset (agilePOR), oscillator (agileRCOSC), comparator (agileCMP), and capless LDO (agileLDO) IPs
“This project showcases the power of our Composa technology and our commitment to close collaboration with our customers,” says Agile CEO Barry Paterson (pictured).
Composa technology automatically generates analogue IP for any foundry and on any process. Each of these IPs can be configured to fit the customer’s exact requirements, allowing for optimal power and performance. The IP can also be delivered digitally wrapped to ease the integration process.
Over the last decade demand for always-on IP has rapidly increased, driven by the surge in smart wearable devices and remote monitoring systems. These rely onthe ability to remain in a low-power state for extended battery life while maintaining the capability to wake up quickly to perform essential functions.
“Our always-on IP subsystem includes all of the analogue circuitry required to minimize quiescent current in always-on applications,” says Agile’s Chris Norrison, “this is crucial for the energy-efficient, responsive SoCs that are needed for the next wave of smart devices.”
